1. Field of the Invention
The present invention relates to an image pick-up apparatus using an image pick-up device of a multi-channel output system.
2. Description of the Related Art
An MOS solid-state image pick-up apparatus often uses a multi-channel output system (multi-line output system) for simultaneously obtaining a plurality of video signal outputs in parallel therewith from a single image pick-up device, as a general method for obtaining a video signal at a high frame rate from an image pick-up device having millions of pixels.
FIG. 1 is an explanatory diagram of a multi-channel output system of a general MOS solid-state pick-up device according to one related art. Referring to FIG. 1, the solid-state pick-up device has (n×n) pixels.
Matrix-arranged pixels P11 to Pnn are divided into four areas. A divided-area-1 has an area ranging from P11 to Paa, a divided-area-2 has an area ranging from P1b to Pan, a divided-area-3 has an area ranging from Pb1 to Pna, and a divided-area-4 has an area ranging from Pbb to Pnn.
Signal outputs are obtained from the respective pixels arranged in the respective divided-area-1 to divided-area-4, that is, the signal outputs from the pixels P11 to Paa in the divided-area-1 are obtained by a horizontal reading circuit (also referred to as a horizontal scanning circuit) 1 and a vertical scanning circuit 5. The signal outputs from the pixels P1b to Pan in the divided-area-2 are obtained by a horizontal reading circuit 2 and the vertical scanning circuit 5. The signal outputs from the pixels Pb1 to Pna in the divided-area-3 are obtained by a horizontal reading circuit 3 and a vertical scanning circuit 6. The signal outputs from the pixels Pbb to Pnn in the divided-area-4 are obtained by a horizontal reading circuit 4 and the vertical scanning circuit 6.
FIG. 2 shows an image pick-up apparatus for processing a plurality of video signal outputs as obtained above according to the one related art. The signals from the horizontal reading circuits 1 to 4 are respectively supplied to signal processing units 7 to 10. The signal processing units 7 to 10 have the same structure and comprise an amplifier and an A/D converter, respectively. In the respective signal processing units 7 to 10, the input signals are amplified by the amplifiers, the amplified signals are converted into digital signals by the A/D converters, and the digital signals are then supplied to an image memory 11. The image memory 11 stores and holds the signals from the signal processing units 7 to 10, and supplies the stored signals to a video signal processing unit (not shown) at the latter stage. The image memory 11 combines respective pixel signals in the divided-area-1 to divided-area-4, thus forming one image.
In the solid-state image pick-up device of the multi-line output system, the pixels at the boundary of the respective divided areas are included in both the adjacent divided areas and are overlappingly read. Then, the read pixels are averaged, to equalize the image quality at the boundary of the respective divided areas. One of the above-mentioned image pick-up devices is disclosed in Japanese Unexamined Patent Application Publication No. 2000-209503 (Patent Document 1).
FIG. 3 is an explanatory diagram showing the image pick-up device disclosed in the Patent Document 1. The image pick-up device shown in FIG. 3 is a general MOS solid-state pick-up device.
The pixel arrangement of the image pick-up device shown in FIG. 3 is the same as that shown in FIG. 1. In the image pick-up device shown in FIG. 1, the respective pixels are included in one of the divided areas. However, the divided areas do not include any common pixel. On the other hand, in the image pick-up device shown in FIG. 3, the adjacent divided areas include common pixels. That is, in the example shown in FIG. 3, the divided-area-1 comprises pixels P11 to Pbb, the divided-area-2 comprises pixels P1a to Pbn, the divided-area-3 comprises pixels Pa1 to Pnb, and the divided-area-4 comprises pixels Paa to Pnn.
Horizontal reading circuits 15 to 18 read the respective pixels in the divided-area-1 to divided-area-4. For example, the signals of the pixels Paa, Pab, Pba, and Pbb are outputted from the entire horizontal reading circuits 15 to 18. The signals of the pixels Pa1 and Pb1 are outputted from the horizontal reading circuits 15 and 17. The signals from the overlappingly-read pixels are averaged, thus to equalize the image quality at the boundary of the divided areas.